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INTEGRATED CIRCUITS
80C552/83C552 Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
Product data Supersedes data of 1998 Aug 13 2002 Sep 03
Philips Semiconductors
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
FEATURES * 80C51 central processing unit * 8k x 8 ROM expandable externally to 64 kbytes * ROM code protection * An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
DESCRIPTION
The 80C552/83C552 (hereafter generically referred to as 8XC552) Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC552 has the same instruction set as the 80C51. Three versions of the derivative exist: * 83C552--8 kbytes mask programmable ROM
* * * * * * * * * * *
Two standard 16-bit timer/counters 256 x 8 RAM, expandable externally to 64 kbytes Capable of producing eight synchronized, timed outputs A 10-bit ADC with eight multiplexed analog inputs Two 8-bit resolution, pulse width modulation outputs Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs I2C-bus serial I/O port with byte oriented master and slave functions Full-duplex UART compatible with the standard 80C51 On-chip watchdog timer Three speed ranges: - 3.5 to 16 MHz - 3.5 to 24 MHz (ROM, ROMless only) Three operating ambient temperature ranges: - P83C552xBx: 0 C to +70 C - P83C552xFx: -40 C to +85 C (XTAL frequency max. 24 MHz) - P83C552xHx: -40 C to +125 C (XTAL frequency max. 16 MHz)
* *
80C552--ROMless version of the 83C552 87C552--8 kbytes EPROM (described in a separate chapter)
The 8XC552 contains a non-volatile 8k x 8 read-only program memory (83C552), a volatile 256 x 8 read/write data memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a 15-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC pulse width modulated interface, two serial interfaces (UART and I2C-bus), a "watchdog" timer and on-chip oscillator and timing circuits. For systems that require extra capability, the 8XC552 can be expanded using standard TTL compatible memories and logic. In addition, the 8XC552 has two software selectable modes of power reduction--idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial ports, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz) crystal, 58% of the instructions are executed in 0.75 s (0.5 s) and 40% in 1.5 s (1 s). Multiply and divide instructions require 3 s (2 s).
LOGIC SYMBOL
VSS VDD XTAL1 XTAL2 EA ALE PSEN AVSS AVDD AVref+ AVref- STADC PWM0 PWM1
PORT 0
LOW ORDER ADDRESS AND DATA BUS
ADC0-7 PORT 5
CT0I CT1I CT2I CT3I T2 RT2 SCL SDA
PORT 2
PORT 1
HIGH ORDER ADDRESS AND DATA BUS
CMSR0-5 PORT 4 RxD/DATA TxD/CLOCK INT0 INT1 T0 T1 WR RD
CMT0 CMT1 RST EW
PORT 3
SU01691
2002 Sep 03
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853-1467 28849
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
PIN CONFIGURATIONS Plastic Leaded Chip Carrier
P4.2/CMSR2 P4.1/CMSR1 P4.0/CMSR0 P5.0/ADC0 P5.4/ADC4 P5.5/ADC5 P5.6/ADC6 P5.1/ADC1 P5.2/ADC2 P5.3/ADC3 P5.7/ADC7 62
PWM1
PWM0
STADC
9 P4.3/CMSR3 10 P4.4/CMSR4 11
8
7
6
5
4
3
2
V DD
EW
1
68
67
66
65
64
63
61 60 AVSS 59 AVREF+ 58 AVREF- 57 P0.0/AD0 56 P0.1/AD1 55 P0.2/AD2 54 P0.3/AD3 53 P0.4/AD4
P4.5/CMSR5 12 P4.6/CMT0 13 P4.7/CMT1 14 RST 15 P1.0/CT0I 16 P1.1/CT1I 17 P1.2/CT2I 18 P1.3/CT3I 19 P1.4/T2 20 P1.5/RT2 21 P1.6/SCL 22 P1.7/SDA 23 P3.0/RxD 24 P3.1/TxD 25 P3.2/INT0 26 27 P3.3/INT1 28 P3.4/T0 29 P3.5/T1 30 P3.6/WR 31 P3.7/RD 32 NC* 33 NC* 34 XTAL2 35 XTAL1 36 VSS 37 VSS 38 NC* 39 P2.0/A08 40 P2.1/A09 41 P2.2/A10 42 P2.3/A11 43 P2.4/A12
PLASTIC LEADED CHIP CARRIER
AVDD 52 P0.5/AD5 51 P0.6/AD6 50 P0.7/AD7 49 EA 48 ALE 47 PSEN 46 P2.7/A15 45 P2.6/A14 44 P2.5/A13
SU00932
* Do not connect.
2002 Sep 03
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
Plastic Quad Flat Pack
P4.0/SMSR0 P5.3/ADC3 P5.4/ADC4 P5.5/ADC5 66 P5.0/ADC0 P5.1/ADC1 P5.2/ADC2 P5.6/ADC6 65 64 P5.7/ADC7 63 AVDD 62 NC* 61 AVSS 60 AVREF+ 59 AVREF- 58 P0.0/AD0 57 P0.1/AD1 56 P0.2/AD2 55 P0.3/AD3 54 P0.4/AD4 53 P0.5/AD5
PWM1
PWM0
STADC
NC*
NC*
80 P4.1/CMSR1 P4.2/CMSR2 NC* P4.3/CMSR3 P4.4/CMSR4 P4.5/CMSR5 P4.6/CMT0 P4.7/CMT1 RST 1 2 3 4 5 6 7 8 9
79
78
77
76
75
74
73
72
V DD
EW
IC
71
70
69
68
67
P1.0/CT0I 10 P1.1/CT1I 11
P1.2/CT2I 12
PLASTIC QUAD FLAT PACK
P1.3/CT3I 13 52 P0.6/AD6 P1.4/T2 14 P1.5/RT2 15 P1.6/SCL 16 P1.7/SDA 17 P3.0/RxD 18 P3.1/TxD 19 P3.2/INT0 20 NC* 21 NC* 22 P3.3/INT1 23 PP3.4/T0 24 25 P3.5/T1 26 P3.6/WR 27 P3.7/RD 28 NC* 29 NC* 30 NC* 31 XTAL2 32 XTAL1 33 IC 34 VSS 35 VSS 36 VSS 37 NC* 38 P2.0/A08 39 P2.1/A09 40 P2.2/A10 51 P0.7/AD7 50 EA
49 ALE 48 PSEN 47 P2.7/A15 46 P2.6/A14 45 P2.5/A13 44 NC* 43 NC* 42 P2.4/A12 41 P2.3/A11
SU00931
* Do not connect. IC = Internally connected (do not use).
2002 Sep 03
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
BLOCK DIAGRAM
T0 3 T1 3 INT0 3 INT1 3 VDD VSS PWM0 PWM1 AVSS AVREF ADC0-7 SDA 5 1 SCL 1
-+
AVDD STADC
XTAL1 XTAL2 EA ALE PSEN 3 3 RD 0 AD0-7 2 A8-15 PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT 8-BIT PORT FOUR 16-BIT CAPTURE LATCHES 16 WR T0, T1 TWO 16-BIT TIMER/EVENT COUNTERS PROGRAM MEMORY 8k x 8 ROM DATA MEMORY 256 x 8 RAM DUAL PWM ADC SERIAL I2C PORT
CPU
80C51 CORE EXCLUDING ROM/RAM
8-BIT INTERNAL BUS
T2 16-BIT TIMER/ EVENT COUNTERS
16
T2 16-BIT COMPARATORS wITH REGISTERS
COMPARATOR OUTPUT SELECTION
T3 WATCHDOG TIMER
3 P0 P1 P2 P3 TxD
3 RxD P5 P4 CT0I-CT3I
1
1 T2 RT2
1
4 CMSR0-CMSR5 CMT0, CMT1 RST EW
0 1 2
ALTERNATE FUNCTION OF PORT 0 ALTERNATE FUNCTION OF PORT 1 ALTERNATE FUNCTION OF PORT 2
3 4 5
ALTERNATE FUNCTION OF PORT 3 ALTERNATE FUNCTION OF PORT 4 ALTERNATE FUNCTION OF PORT 5
SU01692
2002 Sep 03
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
ORDERING INFORMATION
PHILIPS PART ORDER NUMBER PART MARKING ROMless P80C552EBA P80C552EBB P80C552EFA P80C552EFB P80C552EHA P80C552EHB P80C552IBA P80C552IBB P80C552IFA P80C552IFB ROM1 P83C552EBA/xxx P83C552EBB/xxx P83C552EFA/xxx P83C552EFB/xxx P83C552EHA/xxx P83C552EHB/xxx P83C552IBA/xxx P83C552IBB/xxx P83C552IFA/xxx P83C552IFB/xxx SOT188-2 SOT318-2 SOT188-2 SOT318-2 SOT188-2 SOT318-2 SOT188-2 SOT318-2 SOT188-2 SOT318-2 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Quad Flat Pack -40 to +125, Plastic Leaded Chip Carrier -40 to +125, Plastic Quad Flat Pack 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Quad Flat Pack 16 16 16 16 16 16 24 24 24 24 DRAWING NUMBER TEMPERATURE (C) AND PACKAGE FREQ (MHz) ( )
NOTE: 1. xxx denotes the ROM code number. 2. For EPROM device specification, refer to 87C552 datasheet.
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
PIN DESCRIPTION
PIN NO. MNEMONIC VDD STADC PWM0 PWM1 EW P0.0-P0.7 PLCC 2 3 4 5 6 57-50 QFP 72 74 75 76 77 58-51 TYPE I I O O I I/O NAME AND FUNCTION Digital Power Supply: +5 V power supply pin during normal operation, idle and power-down mode. Start ADC Operation: Input starting analog to digital conversion (ADC operation can also be started by software). This pin must not float. Pulse Width Modulation: Output 0. Pulse Width Modulation: Output 1. Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode. This pin must not float. Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 1: 8-bit I/O port. Alternate functions include: (P1.0-P1.5): Quasi-bidirectional port pins. (P1.6, P1.7): Open drain port pins. CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2. T2 (P1.4): T2 event input. RT2 (P1.5): T2 timer reset signal. Rising edge triggered. SCL (P1.6): Serial port clock line I2C-bus. SDA (P1.7): Serial port data line I2C-bus. Port 1 is also used to input the lower order address byte during EPROM programming and verification. A0 is on P1.0, etc. Port 2: 8-bit quasi-bidirectional I/O port. Alternate function: High-order address byte for external memory (A08-A15). Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include: RxD(P3.0): Serial input port. TxD (P3.1): Serial output port. INT0 (P3.2): External interrupt. INT1 (P3.3): External interrupt. T0 (P3.4): Timer 0 external input. T1 (P3.5): Timer 1 external input. WR (P3.6): External data memory write strobe. RD (P3.7): External data memory read strobe. I/O O O I I/O I Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include: CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with timer T2. CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2. Port 5: 8-bit input port. ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC. Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3 overflows. Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the internal clock generator. Receives the external clock signal when an external oscillator is used. Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit when an external clock is used.
P1.0-P1.7
16-23 16-21 22-23 16-19 20 21 22 23
10-17 10-15 16-17 10-13 14 15 16 17
I/O I/O I/O I I I I/O I/O
P2.0-P2.7 P3.0-P3.7
39-46 24-31 24 25 26 27 28 29 30 31
38-42, 45-47 18-20, 23-27 18 19 20 23 24 25 26 27 80, 1-2 4-8 80, 1-2 4-6 7, 8 71-64, 9 32
I/O I/O
P4.0-P4.7
7-14 7-12 13, 14
P5.0-P5.7 RST XTAL1
68-62, 1 15 35
XTAL2
34
31
O
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
PIN DESCRIPTION (Continued)
PIN NO. MNEMONIC VSS PSEN ALE PLCC 36, 37 47 48 QFP 34-36 48 49 TYPE I O O Two Digital ground pins. Program Store Enable: Active-low read strobe to external program memory. Address Latch Enable: Latches the low byte of the address during accesses to external memory. It is activated every six oscillator periods. During an external data memory access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles CMOS inputs without an external pull-up. External Access: When EA is held at TTL level high, the CPU executes out of the internal program ROM provided the program counter is less than 8192. When EA is held at TTL low level, the CPU executes out of external program memory. EA is not allowed to float. Analog to Digital Conversion Reference Resistor: Low-end. Analog to Digital Conversion Reference Resistor: High-end. Analog Ground Analog Power Supply NAME AND FUNCTION
EA
49
50
I
AVREF- AVREF+ AVSS AVDD
58 59 60 61
59 60 61 63
I I I I
NOTE: 1. To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher or lower than VDD + 0.5 V or VSS - 0.5 V, respectively.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol, page 2. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register PCON. Table 1 shows the state of the I/O ports during low current operating modes.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VDD and RST must come up at the same time for a proper start-up.
ROM CODE PROTECTION (83C552)
The 83C552 has an additional security feature. ROM code protection may be selected by setting a mask-programmable security bit (i.e., user dependent). This feature may be requested during ROM code submission. When selected, the ROM code is protected and cannot be read out at any time by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only instructions that have access to program code in the internal or external program memory. The EA input is latched during RESET and is "don't care" after RESET (also if the security bit is not set). This implementation prevents reading internal program code by switching from external program memory to internal program memory during a MOVC instruction or any other instruction that uses immediate data.
IDLE MODE
In the idle mode, the CPU puts itself to sleep while some of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt
Table 1. External Pin Status During Idle and Power-Down Modes
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data PORT 4 Data Data Data Data PWM0/ PWM1 1 1 1 1
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
Serial Control Register (S1CON) - See Table 2
S1CON (D8H) CR2 ENS1 STA STO SI AA CR1 CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
BIT FREQUENCY (kHz) AT fOSC CR2 0 0 0 0 1 1 1 1 CR1 0 0 1 1 0 0 1 1 CR0 0 1 0 1 0 1 0 1 6 MHZ 23 27 31 37 6.25 50 100 0.24 < 62.5 0 < 255 12 MHz 47 54 63 75 12.5 100 200 0.49 < 62.5 0 < 254 16 MHz 62.5 71 83.3 100 17 133 1 267 1 0.65 < 55.6 0 < 253 24 MHz2 94 107 1 125 1 150 1 25 200 1 400 1 0.98 < 50.0 0 <251 fOSC DIVIDED BY 256 224 192 160 960 120 60 96 x (256 - (reload value Timer 1)) reload value Timer 1 in Mode 2.
NOTES: 1. These frequencies exceed the upper limit of 100kHz of the I2C-bus specification and cannot be used in an I2C-bus application. 2. At fOSC = 24 MHz the maximum I2C bus rate of 100kHz cannot be realized due to the fixed divider rates.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Storage temperature range Voltage on any other pin to VSS Input, output DC current on any single I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING -65 to +150 -0.5 to +6.5 5.0 1.0 UNIT C V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V) TYPE P83(0)C552EBx P83(0)C552EFx P83(0)C552EHx P83(0)C552IBx P83(0)C552IFx MIN 4.5 4.5 4.5 4.5 4.5 MAX 5.5 5.5 5.5 5.5 5.5 FREQUENCY (MHz) MIN 3.5 3.5 3.5 3.5 3.5 MAX 16 16 16 24 24 TEMPERATURE RANGE (C) 0 to +70 -40 to +85 -40 to +125 0 to +70 -40 to +85
2002 Sep 03
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0 V; VDD, AVDD = 5 V 10% TEST SYMBOL IDD PARAMETER Supply current operating: P83(0)C552EBx P83(0)C552EFx P83(0)C552EHx P83(0)C552IBx P83(0)C552IFx Idle mode: P83(0)C552EBx P83(0)C552EFx P83(0)C552EHx P83(0)C552IBx P83(0)C552IFx Power-down current: P83(0)C552xBx P83(0)C552xFx P83(0)C552xHx Inputs VIL VIL1 VIL2 VIH VIH1 VIH2 IIL ITL IIL1 IIL2 IIL3 Outputs VOL VOL1 VOL2 VOH Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 Output low voltage, P1.6/SCL, P1.7/SDA Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA IOL = 1.6mA7 IOL = 3.2mA7 IOL = 3.0mA7 -IOH = 60A -IOH = 25A -IOH = 10A -IOH = 400A -IOH = 150A -IOH = 40A -IOH = 400A -IOH = 120A Test freq = 1 MHz, Tamb = 25 C 2.4 0.75VDD 0.9VDD 2.4 0.75VDD 0.9VDD 2.4 0.8VDD 50 150 10 0.45 0.45 0.4 V V V V V V V V V V V k pF Input low voltage, except EA, P1.6, P1.7 Input low voltage to EA Input low voltage to P1.6/SCL, P1.7/SDA5 -0.5 -0.5 -0.5 0.2VDD+0.9 0.7VDD 0.7VDD VIN = 0.45 V See note 6 0.45 V < VI < VDD 0 V < VI < 6 V 0 V < VDD < 5.5 V 0.45 V < VI < VDD 0.2VDD-0.1 0.2VDD-0.3 0.3VDD VDD+0.5 VDD+0.5 6.0 -50 -650 10 10 1 V V V V V V A A A A A CONDITIONS See notes 1 and 2 fOSC = 16 MHz fOSC = 16 MHz fOSC = 16 MHz fOSC = 24 MHz fOSC = 24 MHz See notes 1 and 3 fOSC = 16 MHz fOSC = 16 MHz fOSC = 16 MHz fOSC = 24 MHz fOSC = 24 MHz See notes 1 and 4; 2 V < VPD < VDD max 50 50 150 MIN LIMITS MAX 45 45 40 55 55 10 10 9 12.5 12.5 UNIT mA mA mA mA mA mA mA mA mA mA
IID
IPD
A A A
Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA Input high voltage, XTAL1, RST Input high voltage, P1.6/SCL, P1.7/SDA5 Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 Input leakage current, port 0, EA, STADC, EW Input leakage current, P1.6/SCL, P1.7/SDA Input leakage current, port 5
VOH1
Output high voltage (port 0 in external bus mode, ALE, PSEN PWM0, PWM1)8 PSEN, PWM0 Output high voltage (RST) Internal reset pull-down resistor Pin capacitance
VOH2 RRST CIO
2002 Sep 03
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Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST SYMBOL Analog Inputs AIDD AIID Analog supply current: operating: (16 MHz) Analog supply current: operating: (24 MHz) Idle mode: P83(0)C552EBx P83(0)C552EFx P83(0)C552EHx P83(0)C552IBx P83(0)C552IFx Power-down mode: P83(0)C552xBx P83(0)C552xFx P83(0)C552xHx AVIN AVREF Analog input voltage Reference voltage: AVREF- AVREF+ Resistance between AVREF+ and AVREF- Analog input capacitance Sampling time Conversion time (including sampling time) Differential non-linearity10, 11, 12 Integral non-linearity10, 13 Offset error10, 14 error10, 16 517 Gain error10, 15 Absolute voltage AVSS-0.2 AVSS-0.2 AVDD+0.2 10 50 15 8tCY 50tCY 1 2 2 0.4 3 1 2 V < AVPD < AVDD max 50 50 100 AVDD+0.2 A A A V V V k pF s s LSB LSB LSB % LSB LSB Port 5 = 0 to AVDD Port 5 = 0 to AVDD 1.2 1.0 50 50 100 50 50 mA mA A A A A A PARAMETER CONDITIONS MIN LIMITS MAX UNIT
AIPD
RREF CIA tADS tADC DLe ILe OSe Ge Ae MCTC
Channel to channel matching
Ct Crosstalk between inputs of port 0-100kHz -60 dB NOTES FOR DC ELECTRICAL CHARACTERISTICS: 1. See Figures 10 through 15 for IDD test conditions. 2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS. 3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10 ns; VIL = VSS + 0.5 V; VIH = VDD - 0.5 V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS. 4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = XTAL1 = VSS. 5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 1.5 V will be recognized as a logic 0 while an input voltage above 3.0 V will be recognized as a logic 1. 6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 8. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address bits are stabilizing. 9. The following condition must not be exceeded: VDD - 0.2 V < AVDD < VDD + 0.2 V. 10. Conditions: AVREF- = 0 V; AVDD = 5.0 V, AVREF+ (80C552, 83C552) = 5.12 V. ADC is monotonic with no missing codes. Measurement by continuous conversion of AVIN = -20 mV to 5.12 V in steps of 0.5 mV. 11. The differential non-linearity (DLe) is the difference between the actual step width and the ideal step width. (See Figure 1.) 12. The ADC is monotonic; there are no missing codes. 13. The integral non-linearity (ILe) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (See Figure 1.) 2002 Sep 03 11
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
14. The offset error (OSe) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (See Figure 1.) 15. The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error), and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.) 16. The absolute voltage error (Ae) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. 17. This should be considered when both analog and digital signals are simultaneously input to port 5.
Offset error OSe 1023
Gain error Ge
1022
1021
1020
1019
1018 (2)
7 Code Out 6 (1)
5 (5) 4 (4) 3 (3) 2
1
1 LSB (ideal)
0 1 Offset error OSe (1) (2) (3) (4) (5) Example of an actual transfer curve. The ideal transfer curve. Differential non-linearity (DLe). Integral non-linearity (ILe). Center of a step of the actual transfer curve. 1 LSB = 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
AVIN (LSBideal)
AVREF+
- AVREF-
1024
SU01693
Figure 1. ADC Conversion Characteristic
2002 Sep 03
12
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
AC ELECTRICAL CHARACTERISTICS1, 2
16 MHz version
16 MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX 5 5 5 5 6 6 6 6 High time4 Low time4 Rise time4 Fall time4 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 0.75 492 8 0 20 20 20 20 12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133 20 20 20 20 ns ns ns ns s ns ns ns ns 3 4 3 3 3 3 3 3, 4 3, 4 4 4 4 3 3, 4 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data before WR Data hold after WR RD low to address float RD or WR high to ALE high 23 138 120 3 288 13 0 103 tCLCL-40 0 55 350 398 238 3tCLCL-50 4tCLCL-130 tCLCL-60 7tCLCL-150 tCLCL-50 0 tCLCL+40 275 275 148 0 2tCLCL-70 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 38 208 10 23 143 83 0 tCLCL-25 5tCLCL-105 10 85 8 28 150 tCLCL-40 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-55 tCLCL-35 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
Serial Timing - Shift Register Mode4 (Test Conditions: Tamb = 0 C to +70 C; VSS = 0 V; Load Capacitance = 80 pF)
tXHDV 6 Clock rising edge to input data valid 492 NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. tCLCL = 1/fOSC = one oscillator clock period. tCLCL = 83.3ns at fOSC = 12 MHz. tCLCL = 62.5ns at fOSC = 16 MHz. 4. These values are characterized but not 100% production tested.
2002 Sep 03
13
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
AC ELECTRICAL CHARACTERISTICS (Continued)1, 2
24 MHz version
24 MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tDW tWHQX tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL tXLXL tQVXH tXHQX tXHDX 5 5 5 5 6 6 6 6 High time3 Low time3 Rise time3 Fall time3 0.5 283 23 0 17 17 5 5 12tCLCL 10tCLCL-133 2tCLCL-60 0 10tCLCL-133 17 17 20 20 ns ns ns ns s ns ns ns ns 3 4 3 3 3 3 3 3, 4 3, 4 4 4 4 3 3, 4 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RDxs ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data before WR Data hold after WR RD low to address float RD or WR high to ALE high 17 75 92 12 162 17 0 67 tCLCL-25 0 55 183 210 175 3tCLCL-50 4tCLCL-75 tCLCL-30 7tCLCL-130 tCLCL-25 0 tCLCL+25 150 150 118 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-90 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 2 2 2 2 2 2 2 2 2 2 2 2 PARAMETER Oscillator frequency ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 17 128 10 17 80 65 0 tCLCL-25 5tCLCL-80 10 43 17 17 102 tCLCL-25 3tCLCL-45 3tCLCL-60 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 MAX 24 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
Serial Timing - Shift Register Mode3 (Test Conditions: Tamb = 0 C to +70 C; VSS = 0 V; Load Capacitance = 80 pF) Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge
tXHDV 6 Clock rising edge to input data valid 283 NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. These values are characterized but not 100% production tested. 4. tCLCL = 1/fOSC = one oscillator clock period. tCLCL = 41.7ns at fOSC = 24 MHz.
2002 Sep 03
14
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL I2C Interface (Refer to Figure 9) tHD;STA tLOW tHIGH tRC tFC tSU;DAT1 tSU;DAT2 tSU;DAT3 tHD;DAT tSU;STA tSU;STO tBUF tRD START condition hold time SCL low time SCL high time SCL rise time SCL fall time Data set-up time SDA set-up time (before rep. START cond.) SDA set-up time (before STOP cond.) Data hold time Repeated START set-up time STOP condition set-up time Bus free time SDA rise time 14 tCLCL 16 tCLCL 14 tCLCL 1 s 0.3 s 250ns 250ns 250ns 0ns 14 tCLCL 14 tCLCL 14 tCLCL 1 s > 4.0 s 1 > 4.7 s 1 > 4.0 s 1 -2 < 0.3 s 3 > 20 tCLCL - tRD > 1 s 1 > 8 tCLCL > 8 tCLCL - tFC > 4.7 s 1 > 4.0 s 1 > 4.7 s 1 -2 PARAMETER INPUT OUTPUT
tFD SDA fall time 0.3 s < 0.3 s 3 NOTES: 1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1 s. 3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 62 ns, 42 ns < tCLCL < 285 ns (16 MHz, 24 MHz > fOSC > 3.5 MHz) the SI01 interface meets the I2C-bus specification for bit-rates up to 100 kbit/s.
2002 Sep 03
15
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN tLHLL
ALE
Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low.
tAVLL
PSEN
tLLPL tLLIV
tPLPH
tPLIV tLLAX tPLAZ tPXIX
INSTR IN
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A8-A15 A8-A15
SU01694
Figure 2. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A8-A15 FROM PCH
SU01695
Figure 3. External Data Memory Read Cycle
2002 Sep 03
16
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
A0-A7 FROM RI OR DPL
tQVWX tDW
DATA OUT
tWHQX
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
SU01696
Figure 4. External Data Memory Write Cycle tr VIH1
0.8 V
tHIGH VIH1
0.8 V
tf VIH1 VIH1
0.8 V
0.8 V
tLOW tCLCL Figure 5. External Clock Drive XTAL1
INSTRUCTION ALE 0 1 2 3 4 5 6 7 8
SU01697
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1
2
3
4
5
6
7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI SU01678
Figure 6. Shift Register Mode Timing
2002 Sep 03
17
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
VDD-0.5
0.2 VDD+0.9 VLOAD 0.2 VDD-0.1
VLOAD+0.1 V VLOAD-0.1 V
TIMING REFERENCE POINTS
VOH-0.1 V VOL+0.1 V
0.45 V NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT VDD-0.5 FOR A LOGIC `1' AND 0.45 V FOR A LOGIC `0'. TIMING MEASUREMENTS ARE MADE AT VIH MIN FOR A LOGIC `1' AND VIL MAX FOR A LOGIC `0'.
SU01699
NOTE: FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A 100 mV CHANGE FROM THE LOADED VOH/VOL LEVEL OCCURS. IOH/IOL > + 20mA. SU01700
Figure 7. AC Testing Input/Output
Figure 8. Float Waveform
repeated START condition
START or repeated START condition tRD SDA (INPUT/OUTPUT) STOP condition
tSU;STA
START condition
0.7 VCC 0.3 VCC tBUF tFD tRC tFC tSU;STO 0.7 VCC 0.3 VCC tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tHD;DAT tSU;DAT2
SCL (INPUT/OUTPUT)
SU01701
Figure 9. Timing SIO1 (I2C) Interface
2002 Sep 03
18
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
50 (1) 40
30 IDD, ID mA 20 (2)
10
(3) (4)
0 0 4 8 f (MHz) NOTE: These values are valid only within the frequency specifications of the device under test. 12 16 (1) (2) (3) (4) Maximum operating mode; VDD = 6 V Maximum operating mode; VDD = 4 V Maximum idle mode; VDD = 6 V Maximum idle mode; VDD = 4 V
SU01702
Figure 10. 16 MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
60 (1) 50 (2) 40
IDD, ID mA
30
20
(3) 10 (4)
0 0 4 8 f (MHz) 12 16 20 24 (1) 5.5 V (2) 4.5 (3) V (4) Maximum operating mode; VDD = Maximum operating mode; VDD = Maximum idle mode; VDD = 5.5 V Maximum idle mode; VDD = 4.5 V
NOTE: These values are valid only within the frequency specifications of the device under test.
SU01703
Figure 11. 24 MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (fOSC)
2002 Sep 03
19
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
VDD IDD P1.6 P1.7 VDD RST STADC (NC) CLOCK SIGNAL XTAL2 XTAL1 AVSS VSS AVref- P0 EA EW VDD VDD
VDD
VDD-0.5 0.5 V
0.7VDD 0.2VDD-0.1
tCHCL
tCLCX
tCHCX tCLCH tCLCL
SU01704
SU01706
Figure 12. IDD Test Condition, Active Mode All other pins are disconnected1
VDD IDD P1.6 P1.7 RST STADC P0 VDD VDD VDD
Figure 14. Clock Signal Waveform for IDD Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VDD P1.6 P1.7 RST STADC P0 IDD VDD VDD
VDD
(NC) CLOCK SIGNAL
XTAL2 XTAL1
EW EA AVSS (NC) XTAL2 XTAL1 VSS
EW EA AVSS AVref-
VSS
AVref-
SU01705 SU01707
Figure 13. IDD Test Condition, Idle Mode All other pins are disconnected2
Figure 15. IDD Test Condition, Power Down Mode All other pins are disconnected. VDD = 2 V to 5.5 V3
NOTES: 1. Active Mode: a. The following pins must be forced to VDD: EA, RST, Port 0, and EW. b. The following pins must be forced to VSS: STADC, AVss, and AVref-. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. d. The following pins must be disconnected: XTAL2 and all pins not specified above. 2. Idle Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, AVss,, AVref-, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above. 3. Power Down Mode: a. The following pins must be forced to VDD: Port 0 and EW. b. The following pins must be forced to VSS: RST, STADC, XTAL1, AVss,, AVref-, and EA. c. Ports 1.6 and 1.7 should be connected to VDD through resistors of sufficiently high value such that the sink current into these pins cannot exceed the IOL1 spec of these pins. These pins must not have logic 0 written to them prior to this measurement. d. The following pins must be disconnected: XTAL2 and all pins not specified above.
2002 Sep 03
20
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
PLCC68: plastic leaded chip carrier; 68 leads
SOT188-2
2002 Sep 03
21
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT318-2
2002 Sep 03
22
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM
80C552/83C552
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 09-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 10294
Philips Semiconductors
2002 Sep 03 23

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